The present invention relates to integrated circuit (IC) packaging and, more particularly, to a multi-form IC package.
There are many conventional types of IC packages. Most conventional IC packages include at least (i) an IC die, (ii) a conductive interface for electrically connecting the die to other electronic components, such as, for example, a printed circuit board (PCB), and (iii) an encapsulant enclosing the die to protect the die and keep the die attached to the conductive interface. The conductive interface is either a lead frame or a substrate with conductive traces.
Conventional package types include, for example, dual in-line package (DIP), quad flat-pack (QFP), quad flat-pack no-lead (QFN), ball-grid array (BGA), and pin-grid array (PGA). The selection of a particular package type for a particular application depends on multiple factors. Some applications require a relatively large number of input/output (I/O) interconnects for the IC device. For some of those applications, increasing the density of I/O interconnects can increase the utility of a chip but at the expense of production cost. As used herein, the term “chip” refers to a packaged, singulated, IC device.